The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a circuit for latching data on a data line of a data output path, and a related data latching method for the semiconductor memory device.
In the read operation of general semiconductor memory devices, e.g., synchronous DRAMs, row addresses and column addresses are specified to access a given memory cell. Column address transition is detected by a circuit that provides timing pulses for enabling a data output register after a predetermined delay time. The delay time is necessary for precharging, address decoding, and a sensing or driving operation, and results in it taking a long time to perform a read command. The data latched by the data output register is data of a memory cell selected from a memory cell array block.
A data output path includes sense-amplifiers positioned at the ends of a memory cell array for amplifying the data read from a memory cell. The data amplified by the sense-amplifiers is transmitted to the data output register through a data line. The data output register is positioned near input/output pads of a chip. Since the sense-amplifiers and the data output register are spaced apart from each other, a transmission delay is caused between the valid window of the data read from the memory cell and the time at which the data is latched by the data output register.
Newly read data must be latched after the data previously latched from the memory cell array is stored in the data output register. However, if the data is read later than the timing pulse that enables the data output register and is loaded on the data line with a transmission delay, then the read data may be lost. In other words, since the data output register cannot latch the data during the valid window of the previously read data, the previous data is lost.
The loss of the previous data causes malfunctions of synchronous DRAMs. Therefore, when latching the data on a data line of a data output path leading to the data output register of a synchronous DRAM, the data output register must latch the data without losing of previous data.